A device isolation layer is formed on a semiconductor substrate in order to define active regions and electrically isolate the active regions from each other. As a method of forming the device isolation layer, local oxidation of silicon (LOCOS) technique and trench isolation technique are commonly utilized. Since a semiconductor substrate is locally subject to thermal oxidation to form a field oxide layer, LOCOS is a relatively simple process. As the integration level of semiconductor devices increases, an abnormal feature on the oxide layer referred to as a “bird's beak” or poor planarity caused by the LOCOS process have become serious problems. Accordingly, the trench isolation technique has widely been utilized.
In the trench isolation technique, an etching mask for a trench is formed on a semiconductor substrate. Using the etching mask, the semiconductor substrate is etched to form a trench, which is then filled with an insulating layer. In the following wet etching process, the insulating layer is etched, which could cause a deterioration of the characteristics of the device isolation layer. Accordingly, the insulating layer is densified for preventing the deterioration. The densification is carried out by annealing the insulating layer in oxygen ambient at a temperature of 900° C.˜1200° C. for an hour.
Since the densification is carried out at a high temperature, this changes the volumes an insulating layer formed in a trench and a semiconductor substrate vary. The thermal expansion ratio of the insulating layer is different from that of the semiconductor substrate, so that stress is applied to the trench inner wall that serves as an interface therebetween.
U.S. Pat. No. 6,037,237 discloses a method of forming an insulating layer composed of stacked layers whose stress characteristics are different from each other when the insulating layer is formed to fill a trench. According to this approach, an insulating layer having a compressive stress characteristic, and an insulating layer having a tensile stress characteristic, for example, a USG (undoped silicate glass) layer and a PTEOS (plasma tetraethylorthosilicate) layer, or an HDP (high density plasma) layer and the PTEOS layer, are stacked to reduce stress applied to the semiconductor substrate during the densification. An upper insulating layer is made of an insulator of favorable planarization characteristic, easily carrying out the following planarization etching process.
Although the insulating layer of a stack structure is formed for reducing the stress, the following densification still puts a burden on the overall process. That is, stress created in the high thermal annealing process cannot entirely be removed, and therefore causes a declination in productivity.